A non-volatile memory device retains data even after power to the device is terminated. One particular type of non-volatile memory device is an electrically erasable programmable read only memory (EEPROM) device. In an EEPROM device, programming and erasing are accomplished by transferring electrons to and from a floating gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating gate electrode and an underlying substrate. Typically, electron transfer is carried out by either hot electron injection or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating gate electrode by a control gate electrode, also known as a programming region. The control gate electrode or programming region is capacitively coupled to the floating gate electrode such that a voltage applied to the programming region is coupled to the floating gate electrode.
A traditional EEPROM device utilizes the floating gate, in a field effect transistor structure, positioned over but insulated from a channel region in the semiconductor substrate, and between source and drain regions. A threshold voltage characteristic of the transistor is controlled by an amount of charge that is retained on the floating gate. Thus, a minimum amount of voltage (i.e., the threshold voltage) must be applied to the control gate before the transistor is turned “on,” thus permitting conduction between source and drain regions of the transistor. Conduction is controlled by the amount of charge on the floating gate. A memory transistor is programmed or erased to one of two states by transferring electrons from the substrate channel region, through a tunnel window constructed in the thin dielectric tunnel layer and onto and from the floating gate.
A state of the memory transistor is read by placing an operating voltage across the source and drain with an additional voltage on the control gate of the memory transistor. A level of current flowing between the source and drain is detected to determine whether the device is programmed to be “on” or “off” for a given control gate voltage. A specific single memory transistor cell in a two-dimensional array of EEPROM memory cells is addressed for reading by (1) applying a source-drain voltage to source and drain lines in a column containing the cell being addressed, and; (2) applying a control gate voltage to the control gates in a row containing the cell being addressed.
As discussed, EEPROM memory cells may be erased electrically. One way in which the cell is erased electrically is by transfer of charge from the floating gate to the transistor drain through a thin tunnel dielectric layer. Charge transfer is again accomplished by applying appropriate voltages to the source, drain, and control gate of the floating gate transistor. An array of EEPROM cells is generally referred to as a Flash EEPROM array because an entire array of cells, or a significant group of cells, is erased simultaneously.
As Flash EEPROM arrays become increasingly larger in terms of storage capacity, the semiconductor industry has attempted various ways of reducing a size of individual memory cells, and thus, reducing a size of the entire array. The size reduction however cannot impact reliability nor critical characteristics of the memory device such as standby current. The reduction in size of individual memory cells means an overall reduction in the area of the memory array. With more devices available in a given area, it is critical that each device maintains as low a standby current as possible.
Traditionally, EEPROM cell size has been limited by the required width of the active region. A primary limiting factor in determining the active region width is the size of the tunnel window. Traditionally, the tunnel window is defined by lithography which produces a limitation on a minimum aperture size for the tunnel window. The active area is required by process design rules to extend beyond this minimum aperture size. Consequently, this requirement determines a minimum width of the memory device conduction channel. To achieve a maximum of saturation current through the conduction channel, it is desirable to maximize the ratio of width to length of the memory device.
The lithographic limits in determining the minimum width of the tunnel window also determine a minimum width of the memory device. With the width of the memory device determined, the length of the memory device is also determined. The constraints determined by the feature size of the tunnel window therefore produce a limitation on the scalability of the EEPROM cell and in turn limit the ability to minimize the memory cell size.
It would be desirable to achieve an enhancement to a tunnel window fabrication process which would further reduce the minimum aperture size of the tunnel diode window. A further reduction in the minimum feature size of the tunnel window directly affects the minimum features of a memory device. A further reduction in tunnel window size would enhance the scalability of the EEPROM memory cell. Additionally it would be further desirable to achieve the reduction in minimal feature size while maintaining an extremely low standby current.